The present invention relates to a semiconductor large-scale integrated circuit having a central processing unit (CPU) and a digital signal processing unit, and more specifically to a technology suitably applied to data processing devices, such as microcomputers and digital signal processors, that require high calculation speeds.
An example of a microcomputer, which has mounted on a single chip the central processing unit (CPU) for controlling an entire system and the digital signal processing unit (digital signal processor (DSP)) having a product sum function required for efficient processing of digital signals, is found in xe2x80x9cSH Series Incorporating DSP Functionxe2x80x9d by Kawasaki, et al., Nikkei Electronics, Nov. 23, 1992 issue, no. 568, pp. 99-112.
According to this literature, the digital signal processing unit having the product sum function is able to execute representative calculations of digital signal processing, such as digital filtering, efficiently in a small number of steps.
The conventional digital signal processing unit described in the above literature, though it has a product sum calculator, handles data to be calculated as integer data as in the central processing unit. Data handled in the world of digital signal processing are generally fixed-point or floating-point data. The floating-point data has a data format consisting of mantissa data and exponent data and is totally different from integer data, whereas the fixed-point data looks very similar to integer data except that the binary point position is different. Actually, the adding and subtracting calculation on the fixed-point data performs basically the same processing as the integer data.
Multiplication, however, uses lower-order words of specified registers as source data in the case of integer data but, in the case of the fixed-point data, uses higher-order words of specified registers, as shown in FIG. 1(a). This is because a part of data closer to the binary point is more important and, as shown in FIG. 1(b), the integer data is regarded to have the binary point to the right of the least significant bit whereas the fixed-point data normally has the point immediately to the right of the most significant bit. Hence, for an integer multiplier to carry out fixed-point multiplication, the source data needs to be shifted from the higher-order side to the lower-order side beforehand. Further, as shown in FIG. 1(c), digit aligning is performed based on the binary point position, producing a one-bit position difference between the integer data and the fixed-point data. This requires the actual program to perform shift processing to correct the bit positional difference.
There is another problem. When data read out from memory or calculation results are stored in memory or output to external devices, the digital signal processing often allows the bit length of such data to have a lower bit precision than during calculation. Hence, the actual digital signal processing unit generally performs data transfer to and from memory or external circuits in single precision words (for example, 16-bit words) and calculations in double precision words (for example, 32-bit words). When transferring data whose bit length is shorter than these calculation precisions, the operations performed on integer data and on fixed-point data greatly differ.
When transferring word data and byte data (8 bits long) whose bit length is short, the calculator dedicated to handling integer data inputs and outputs the lower-order side of a register that stores data. However, the calculator dedicated to handling fixed-point data inputs and outputs the higher-order side of the data. This difference is caused by the differing positions of the binary point. That is, when the bit length of the data to be transferred is shorter than the bit length of the operand to be stored, a part of the data closer to the binary point is more important from the standpoint of data precision and range. This binary point is assumed to be located to the right of the least significant bit in integer data whereas the binary point in fixed-point data is usually located immediately to the right of the most significant bit. This causes the above-mentioned difference in the data handling. As a result, a problem arises that the shift processing must be done each time a calculator designed to handle integer data transfers data whose bit length is shorter than the calculation precision.
If the bit length of data during transfer is set equal to the bit length of data during calculation, no such problem will occur. But transfer of redundant bits raises a problem of requiring an additional bus width and an additional memory capacity for storing data.
An object of the present invention is to provide a data processing device, such as a microcomputer and a digital signal processor, incorporating a central processing unit and a digital signal processing unit that processes fixed-point data.
Another object of the present invention is to prevent the number of processing steps from being increased by the difference in the type of data handled by the calculator and thereby enhance the efficiency of the digital signal processing in the microcomputer and the digital signal processor, which have mounted on a single chip a central processing unit for controlling the whole system and a digital signal processing unit having a product sum function for efficiently processing digital signals.
A further object of the present invention is to eliminate additional shift operations required by the correction of bit positions of multiplication results and by the data transfer, thereby increasing the speed of the digital signal processing.
These and other objects and novel features of the present invention will become apparent from the following description in this specification and the accompanying drawings.
Representative aspects of this invention may be briefly summarized as follows.
(a) The data processing device (1) has mounted on a single semiconductor substrate a CPU (100) and a digital signal processing unit (104) whose operation is controlled by the CPU (100) decoding instructions. The digital signal processing unit (104) has an addition/subtraction circuit (105) for fixed-point data and a multiplier (106) for fixed-point data.
(b) The data processing device (1) has a first processing unit (100) and a second processing unit (104), the first processing unit including a first register (103) and first calculators (101, 102) for performing operations on data contained in the first register (103), the second processing unit including a second register (108) and second calculators (105, 106) for performing operations on data contained in the second register (108). The first processing unit (100) processes integer data and the second processing unit (104) processes fixed-point data.
(c) The digital signal processing unit (104) has a register (108) and calculators (105, 106) for processing data in the register (108). When performing a first instruction for transferring data whose bit length is shorter than the bit length of the register (108) from outside the data processing device to the register (108), the data processing device (104) takes and justifies data to the higher-order side of the register (108) and setting zeros at the redundant lower-order side of the register (108). When performing a second instruction for transferring data whose bit length is shorter than the bit length of the register (108) from the register (108) to the outside of the data processing unit (104), the data processing unit (104) outputs a required bit length of data beginning with the higher-order side of the register (108).
(d) The data processing device (1) has a central processing unit (100) including a calculation circuit (101) that performs arithmetic operation or logic operation; first, second and third address buses (109, 110, 111) to which addresses are selectively transferred from the central processing unit (100); a first memory (115) connected to the first address bus (109) and the second address bus (110) and accessed through an address from the central processing unit (100); a second memory (116) connected to the first address bus (109) and the third address bus (111) and accessed through an address from the central processing unit (100); a first data bus (112) connected to the first and second memories (115, 116) and the central processing unit (100) to transfer data; a second data bus (113) connected to the first memory (115) to transfer data; a third data bus (114) connected to the second memory (116) to transfer data; and a digital signal processing unit (104) connected to the first, second and third data buses (112, 113, 114) and adapted to operate in synchronism with the central processing unit (100). The digital signal processing unit (104) has an addition/subtraction circuit (105) for processing fixed-point data and a multiplier (106) for processing fixed-point data.
(e) The data processing device includes a multiplier (106) which takes in a multiplier and a multiplicand and outputs the result of multiplication of the multiplier and the multiplicand and a shifter (107) that shifts the output of the multiplier. When performing a multiplication operation on integer data, the shifter outputs the output of the multiplier without shifting it. When performing a multiplication operation on fixed-point data, the shifter shifts left the output of the multiplier one bit and sets zero at the least significant bit.
That is, in data transfer between the digital signal processing unit and memories or external circuits, when data whose bit length is shorter than the calculation precision is transferred, the digital signal processing unit is provided with a function to input and output data to and from the higher-order side of the data storage register and a separate data transfer instruction for fixed-point data is provided in addition to the conventional transfer instruction for integer data.
When a fixed-point data transfer instruction is issued and the data received has a shorter bit length than a destination register, it is stored justified to the higher-order side of the destination register, with the lower bits cleared. On the contrary, when data is to be output from a source register, a required number of bits beginning with the highest order of the source register are output. As a result, no additional shift operation needs to be performed.
In microcomputers and digital signal processorsxe2x80x94in which a central processing unit for controlling the entire system and a digital signal processing unit having a product sum function required to process digital signals efficiently are mounted on a single chipxe2x80x94the digital signal processing unit is made a calculation unit to handle fixed-point data and an instruction calling for execution of operation on fixed-point data is provided apart from the conventional integer calculation instruction.
That is, when a fixed-point data multiplication instruction is issued, the calculation unit to perform multiplication has the register output the source data from the higher order side, shifts left the output of the conventional integer data multiplier by one bit and stores it in a specified destination register.